Scaling MOSFET transistors to improve performance results in higher gate leakage as the SiO2 gate dielectric becomes thinner. To address this issue, SiO2 gate dielectric are often replaced with high-k dielectrics. A high-k dielectric is a dielectric featuring a dielectric constant (k) higher than the dielectric constant of SiO2, i.e. k>3.9. High-k dielectrics allow for a larger physical thickness (compared to SiO2) for obtaining a same effective capacitance than can be obtained with a much thinner SiO2 layer. The larger physical thickness of the high-k material can reduce gate leakage currents. Typical examples of high-k dielectrics are Hf-based or Al-based materials (e.g. Hf oxides or Al oxides).
With the introduction of the high-k dielectrics a new problem appeared: Fermi level pinning. The Fermi level pinning effect occurs at the polysilicon (poly-Si)/metal oxide interface and causes high threshold voltages in MOSFET devices. For Hf-based materials, the interfacial Si—Hf bonds create dipoles. This pins the Fermi level just below the poly-Si conduction band and increases the poly-Si depletion of p-doped gates. For Al2O3 gate dielectrics, the Si—O—Al bonds the Fermi level just above the Si valence band. The Al at the interface behaves as a dopant and increases the poly-Si depletion of n-doped gates.
One solution to this problem is the introduction of metal gates. However, it has been proven difficult to identify band-edge metals (metals with either a n-type or a p-type work function (WF)) that are compatible with the conventional CMOS (Complementary Metal-Oxide-Semiconductor) manufacturing process. CMOS can be made using dual metal gates with single or dual dielectrics. In either case, a selective removal of one of the metal gates and/or dielectrics is necessary and adds substantial complexity and costs to the manufacturing process.
Another solution to the problem of Fermi level pinning is to use Fully Silicided (FUSI) gates, without a selective removal of electrode or gate dielectric. However, FUSI gates require different silicide phases on nMOS and pMOS regions. On small devices, the phase or composition of the FUSI gates tends to distribute unevenly, which can result in severe within-wafer threshold voltage (Vt) non-uniformity.